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| preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. october 2007 rev 3 1/71 1 stm32f101x6 stm32f101x8 stm32f101xb access line, advanced arm-based 32-bit mcu with flash memory, six 16-bit timers, adc and seven communication interfaces features core: arm 32-bit cortex?-m3 cpu ? 36 mhz, 45 dmips with 1.25 dmips/mhz ? single-cycle multiplication and hardware division memories ? 32-to-128 kbytes of flash memory ? 6-to-16 kbytes of sram clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr and programmable voltage detector (pvd) ? 4-to-16 mhz high-spe ed quartz oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc ? pll for cpu clock ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers debug mode ? serial wire debug (swd) and jtag interfaces dma ? 7-channel dma controller ? peripherals supported: timers, adc, spis, i 2 cs and usarts 1 12-bit, 1 s a/d converter (16-channel) ? conversion range: 0 to 3.6 v ? temperature sensor up to 80 fast i/o ports ? 26/36/51/80 i/os, all mappable on 16 external interrupt vectors, all 5 v-tolerant except for analog inputs up to 6 timers ? up to three 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter ? 2 watchdog timers (independent and window) ? systick timer: 24-bit downcounter up to 7 communication interfaces ? up to 2 x i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 2 spis (18 mbit/s) ecopack? packages table 1. device summary reference root part number stm32f101x6 stm32f101c6, stm32f101r6, stm32f101t6, stm32f101cbt6 stm32f101x8 stm32f101c8, stm32f101r8 stm32f101v8, stm32f101t8 stm32f101xb stm32f101 rb, stm32f101vb lqfp48 7 x 7 mm lqfp100 14 x 14 mm lqfp64 10 x 10 mm vfqfpn36 6 6 mm www.st.com
contents stm32f101xx 2/71 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 28 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.11 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 46 5.3.12 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.13 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 stm32f101xx contents 3/71 5.3.14 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.15 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1 future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 appendix a important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 a.1 pd0 and pd1 use in output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 a.2 adc auto-injection channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 a.3 adc combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . 68 a.4 voltage glitch on adc input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 list of tables stm32f101xx 4/71 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device features and peripheral counts (stm32f101xx access line) . . . . . . . . . . . . . . . . . 8 table 3. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 11. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 31 table 14. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 32 table 15. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. typical current consumption in sleep mode, code with data processing code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. typical current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. high-speed user external (hse) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 22. lse oscillator characteristics ( flse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 23. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 24. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 25. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 26. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 28. flash endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 29. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 30. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 31. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 32. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 34. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 35. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 36. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 37. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 38. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 39. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 40. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 41. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 42. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 43. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 44. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 stm32f101xx list of tables 5/71 table 45. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 62 table 46. lqpf100 ? 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 63 table 47. lqfp64 ? 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 64 table 48. lqfp48 ? 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 65 table 49. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 50. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 51. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 list of figures stm32f101xx 6/71 list of figures figure 1. stm32f101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. stm32f101xx access line vfqpfn36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. stm32f101xx access line lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. stm32f101xx access line lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. stm32f101xx access line lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled. . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. current consumption in standby mode versus temperature at v dd = 3.3 v to 3.6 v . . . . . 33 figure 15. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. unused i/o pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 20. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 21. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 22. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 23. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 24. spi timing diagram - slave mode and cpha=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 25. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 26. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 27. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 28. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 60 figure 29. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 61 figure 30. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 31. lqpf100 ? 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 32. lqfp64 ? 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33. lqfp48 ? 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 stm32f101xx introduction 7/71 1 introduction this datasheet contains the description of th e stm32f101xx access line family features, pinout, electrical characteristics, mechanical data and ordering information. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10x flash programming reference manual for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual. 2 description the stm32f101xx access line family incorporates the high-performance arm cortex?- m3 32-bit risc core operating at a 36 mhz frequency, high-speed embedded memories (flash memory up to 128kbytes and sram up to 16 kbytes), and an extensive range of enhanced peripherals and i/os connected to two apb buses. all devices offer standard communication interfaces (two i 2 cs, two spis, and up to three usarts), one 12-bit adc and three general purpose 16-bit timers. the stm32f101 family operates in the ? 40 to +85c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows to design low-power applications. the complete stm32f101xx access line family includes devices in 3 different package types: from 36 pins to 100 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the stm32f101xx access line microcontroller family suitable for a wide range of applications: application control and user interface medical and handheld equipment pc peripherals, gaming and gps platforms industrial applications: plc, inverters, printers, and scanners alarm systems, video intercom, and hvac figure 1 shows the general block diagram of the device family. description stm32f101xx 8/71 2.1 device overview table 2. device features and peripheral counts (stm32f101xx access line) peripheral stm32f101tx stm32f101cx stm32f101rx stm32f101vx flash - kbytes 32 64 32 64 128 32 64 128 64 128 sram - kbytes 6 10 6 10 16 6 10 16 10 16 timers general purpose 232332 3 3 communication spi 121221 2 2 i 2 c 121221 2 2 usart 232332 3 3 12-bit synchronized adc number of channels 1 10 channels 1 10 channels 1 16 channels 1 16 channels gpios 26 36 51 80 cpu frequency 36 mhz operating voltage 2.0 to 3.6 v operating temperature ?40 to +85 c packages vfqfpn36 lqfp48 lqfp64 lqfp100 stm32f101xx description 9/71 2.2 overview arm ? cortex tm -m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f101xx access line family having an embedded arm core, is therefore compatible with all arm tools and software. embedded flash memory up to 128 kbytes of embedded flash is available for storing programs and data. embedded sram up to 16 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. nested vectored interrupt controller (nvic) the stm32f101xx access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. description stm32f101xx 10/71 external interrupt/event controller (exti) the external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect external line with pulse width lower than the internal apb2 clock period. up to 80 gpios are connected to the 16 external interrupt lines. clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-16 mhz clock can be selected and is monitored for failure. during such a scenario, it is disabled and software interrupt management follows. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow the configurati on of the ahb frequenc y, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum freque ncy of the ahb and the apb domains is 36 mhz. boot modes at startup, boot pins are used to select one of five boot options: boot from user flash boot from system memory boot from sram the boot loader is located in system memory. it is used to reprogram the flash memory by using the usart. power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. in v dd range (adc is limited at 2.4 v). v bat = 1.8 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. power supply supervisor the device has an integrated power on reset (por)/power down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 9: embedded reset and power control block characteristics for the values of v por/pdr and v pvd . stm32f101xx description 11/71 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop modes power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enable d after reset. it is disabled in standby mode, providing high impedance output. low-power modes the stm32f101xx access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode allows to achieve the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi and the hse rc oscillators are disabled. the vo ltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output or the rtc alarm. standby mode the standby mode allows to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi and the hse rc os cillators are also switched off. afte r entering standby mode, sram and registers content are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. dma the flexible 7-channel general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general purpose timers timx and adc. description stm32f101xx 12/71 rtc (real-time clock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers (ten 16-bit registers) can be used to store data when v dd power is not present. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clo cked by an external 32.768 khz o scillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low power rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated for os, but could al so be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source general purpose timers (timx) there are up to 3 synchronizable standard timers embedded in the stm32f101xx access line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, pwm or one pulse mode output. this gives up to 12 input captures / output compares / pwms on the largest packages. they can work together via the timer link feature for synchronization or event chaining. the counter can be frozen in debug mode. any of the standard timers can be used to generate pwm outputs. each of the timers has independent dma request generations. stm32f101xx description 13/71 i2c bus up to two i2c bus interfaces can operate in multi-master and slave modes. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. universal synchronous/asynchronous receiver transmitter (usart) the available usart interfaces communicate at up to 2.25 mbit/s. they provide hardware management of the cts and rts signals, support irda sir endec, are iso 7816 compliant and have lin master/slave capability. the usart interfaces can be served by the dma controller. serial peripheral interface (spi) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. the hardware crc generation/verification supports basic sd card/mmc modes. both spis can be served by the dma controller. gpios (general purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. adc (analog to digital converter) the 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. temperature sensor the temperature sensor has to generate a linear voltage with any variation in temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. description stm32f101xx 14/71 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded. and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. figure 1. stm32f101xx access line block diagram 1. af = alternate function on i/o port pin. 2. t a = ?40 c to +85 c (junction temperature up to 125 c). temp sen so r pa[ 15:0] exti w w d g nvic 12bit adc1 swd 16af jtdi jtck/swclk jtms/swdio jntrst jtdo nrst v dd = 2 to 3.6v 80af pb[ 15:0] pc[15:0] ahb2 mosi,miso,sck,nss sram 2x(8x16bit) wakeup gpioa gpiob gpioc f max : 36 mhz v ss scl,sda i2c2 v ref+ gp dma tim2 tim3 xtal osc 4-16 mhz xtal 32 khz osc_in osc_out osc32_out osc32_in pll & apb 1 : f max =24 / 36 mhz pclk1 hclk clock managt pclk 2 as af as af volt. reg. 3.3v to 1.8v power backu p i nterf ace as af 16 kb rtc rc 8 mhz cortex m3 cpu usart1 usart2 spi2 7 channels back up reg scl,sda,smba l i2c1 as af rx,tx, cts, rts, usart3 v ref- pd[15:0] gpiod ahb:f max =36 mhz 4 chann els 4 chann els fclk rc 42 khz stand by iwdg @vdd @vbat por / pdr supply @vdda vdda vssa @vdda v bat ck, smartcard as af rx,tx, cts, rts, smart card as af rx,tx, cts, rts, apb2 : f max = 36 mhz nvic spi1 mosi,miso, sck,nss as af if interface @vdda supervision pvd rst int @vdd ahb2 apb2 apb 1 awu tamper-rtc pe[15:0] gpioe flash 128 kb busm atrix 64 bit inte rfac e ibus dbus pbus obl flash trace cont rol ler syst em tim4 4 channels ai14385b traceclk traced[0:3] as as sw/jtag tpiu trace/trig ck, smartcard as af stm32f101xx pin descriptions 15/71 3 pin descriptions figure 2. stm32f101xx access line vfqpfn36 pinout v ss_3 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 36 35 34 33 32 31 30 29 28 v dd_3 1 27 v dd_2 osc_in/pd0 2 26 v ss_2 osc_out/pd1 3 25 pa13 nrst 4 qfn36 24 pa12 v ssa 5 23 pa11 v dda 6 22 pa10 pa0-wkup 7 21 pa 9 pa 1 8 20 pa 8 pa 2 9 19 v dd_1 10 11 12 13 14 15 16 17 18 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 v ss_1 ai14654 pin descriptions stm32f101xx 16/71 figure 3. stm32f101xx access line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe2 pe3 pe4 pe5 pe6 vbat pc13-anti_tamp pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14386 lqfp100 stm32f101xx pin descriptions 17/71 figure 4. stm32f101xx access line lqfp64 pinout figure 5. stm32f101xx access line lqfp48 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc13-anti_tamp pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14387 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 vbat pc13-anti_tamp pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 ai14378 pin descriptions stm32f101xx 18/71 table 3. pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) default alternate functions (3) lqfp48 lqfp64 lqfp100 vfqfpn36 - - 1 - pe2 i/o ft pe2 traceclk - - 2 - pe3 i/o ft pe3 traced0 - - 3 - pe4 i/o ft pe4 traced1 - - 4 - pe5 i/o ft pe5 traced2 - - 5 - pe6 i/o ft pe6 traced3 11 6 - v bat sv bat 2 2 7 - pc13-tamper-rtc (4) i/o pc13 tamper-rtc 3 3 8 - pc14-osc32_in (4) i/o pc14- osc32_in 4 4 9 - pc15-osc32_out (4) i/o pc15- osc32_out --10- v ss_5 sv ss_5 --11- v dd_5 sv dd_5 5 5 12 2 osc_in i osc_in 6 6 13 3 osc_out o osc_out 7 7 14 4 nrst i/o nrst - 8 15 - pc0 i/o pc0 adc_in10 - 9 16 - pc1 i/o pc1 adc_in11 - 10 17 - pc2 i/o pc2 adc_in12 - 11 18 - pc3 i/o pc3 adc_in13 81219 5 v ssa sv ssa --20- v ref- sv ref- --21- v ref+ sv ref+ 91322 6 v dda sv dda 10 14 23 7 pa0-wkup i/o pa0 wkup/usart2_cts (7) / adc_in0/ tim2_ch1_etr (7) 11 15 24 8 pa1 i/o pa1 usart2_rts (7) /adc_in1/ tim2_ch2 (7) 12 16 25 9 pa2 i/o pa2 usart2_tx (7) /adc_in2/ tim2_ch3 (7) 13 17 26 10 pa3 i/o pa3 usart2_rx (7) /adc_in3/ tim2_ch4 (7) -1827 - v ss_4 sv ss_4 stm32f101xx pin descriptions 19/71 -1928 - v dd_4 sv dd_4 14 20 29 11 pa4 i/o pa4 spi1_nss/usart2_ck (7) / adc_in4 15 21 30 12 pa5 i/o pa5 spi1_sck/adc_in5 16 22 31 13 pa6 i/o pa6 spi1_miso/adc_in6/ tim3_ch1 (7) 17 23 32 14 pa7 i/o pa7 spi1_mosi/adc_in7/ tim3_ch2 (7) - 24 33 pc4 i/o pc4 adc_in14 - 25 34 pc5 i/o pc5 adc_in15 18 26 35 15 pb0 i/o pb0 adc_in8/tim3_ch3 (7) 19 27 36 16 pb1 i/o pb1 adc_in9/tim3_ch4 (7) 20 28 37 17 pb2/boot1 i/o ft pb2/boot1 - - 38 - pe7 i/o ft pe7 - - 39 - pe8 i/o ft pe8 - - 40 - pe9 i/o ft pe9 - - 41 - pe10 i/o ft pe10 - - 42 - pe11 i/o ft pe11 - - 43 - pe12 i/o ft pe12 - - 44 - pe13 i/o ft pe13 - - 45 - pe14 i/o ft pe14 - - 46 - pe15 i/o ft pe15 21 29 47 - pb10 i/o ft pb10 i2c2_scl (5) /usart3_tx (5) (7) 22 30 48 - pb11 i/o ft pb11 i2c2_sda (5) /usart3_rx (5) (7) 23 31 49 18 v ss_1 sv ss_1 24 32 50 19 v dd_1 sv dd_1 25 33 51 - pb12 i/o ft pb12 spi2_nss (5) (7) /i2c2_smbal (5) / usart3_ck (5) (7) 26 34 52 - pb13 i/o ft pb13 spi2_sck (5)(7) / usart3_cts (5)(7) 27 35 53 - pb14 i/o ft pb14 spi2_miso (5)(7) / usart3_rts (5)(7) 28 36 54 - pb15 i/o ft pb15 spi2_mosi (5) (7) - - 55 - pd8 i/o ft pd8 table 3. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) default alternate functions (3) lqfp48 lqfp64 lqfp100 vfqfpn36 pin descriptions stm32f101xx 20/71 - - 56 - pd9 i/o ft pd9 - - 57 - pd10 i/o ft pd10 - - 58 - pd11 i/o ft pd11 - - 59 - pd12 i/o ft pd12 - - 60 - pd13 i/o ft pd13 - - 61 - pd14 i/o ft pd14 - - 62 - pd15 i/o ft pd15 - 37 63 - pc6 i/o ft pc6 38 64 - pc7 i/o ft pc7 39 65 - pc8 i/o ft pc8 - 40 66 - pc9 i/o ft pc9 29 41 67 20 pa8 i/o ft pa8 usart1_ck/mco 30 42 68 21 pa9 i/o ft pa9 usart1_tx (7) 31 43 69 22 pa10 i/o ft pa10 usart1_rx (7) 32 44 70 23 pa11 i/o ft pa11 usart1_cts 33 45 71 24 pa12 i/o ft pa12 usart1_rts 34 46 72 25 pa13/jtms/swdio i/o ft jtms-swdio pa13 - - 73 - not connected 35 47 74 26 v ss_2 sv ss_2 36 48 75 27 v dd_2 sv dd_2 37 49 76 28 pa14/jtck/swclk i/o ft jtck/swclk pa14 38 50 77 29 pa15/jtdi i/o ft jtdi pa15 - 51 78 pc10 i/o ft pc10 - 52 79 pc11 i/o ft pc11 - 53 80 pc12 i/o ft pc12 5 5 81 2 pd0 i/o ft osc_in (6) 6 6 82 3 pd1 i/o ft osc_out (6) 54 83 - pd2 i/o ft pd2 tim3_etr - - 84 - pd3 i/o ft pd3 - - 85 - pd4 i/o ft pd4 - - 86 - pd5 i/o ft pd5 - - 87 - pd6 i/o ft pd6 table 3. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) default alternate functions (3) lqfp48 lqfp64 lqfp100 vfqfpn36 stm32f101xx pin descriptions 21/71 - - 88 - pd7 i/o ft pd7 39 55 89 30 pb3/jtdo i/o ft jtdo pb3/traceswo 40 56 90 31 pb4/jntrst i/o ft jntrst pb4 41 57 91 32 pb5 i/o pb5 i2c1_smbal 42 58 92 33 pb6 i/o ft pb6 i2c1_scl (7) /tim4_ch1 (5) (7) 43 59 93 34 pb7 i/o ft pb7 i2c1_sda (7) /tim4_ch2 (5) (7) 44 60 94 35 boot0 i boot0 45 61 95 - pb8 i/o ft pb8 tim4_ch3 (5) (7) 46 62 96 - pb9 i/o ft pb9 tim4_ch4 (5) (7) - - 97 - pe0 i/o ft pe0 tim4_etr (5) - - 98 - pe1 i/o ft pe1 47 63 99 36 v ss_3 sv ss_3 48 64 100 1 v dd_3 sv dd_3 1. i = input, o = output, s = supply, hiz= high impedance. 2. ft= 5 v tolerant. 3. function availability depends on the chos en device. refer to table 2 on page 7. 4. pc13, pc14 and pc15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used only in output 2 mhz mode with a maximum load of 30 pf and only one pin can be put in output mode at a time. 5. available only on devices with a flash me mory density equal or higher than 64 kbytes. 6. the pins number 2 and 3 in the vfqfpn36 package, and 5 and 6 in the lqfp48 and lqfp64 packages are configured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100 package, pd0 and pd1 are avail able by default, so there is no need for remapping. for more details, refer to the alternate function i/o and debug configuration section in the stm32f10xxx reference manual. the use of pd0 and pd1 in output mode is limited as they can only be used at 50 mhz in output mode. 7. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the st m32f10xxx reference manual, available from the stmicroel ectronics website: www.st.com. table 3. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) default alternate functions (3) lqfp48 lqfp64 lqfp100 vfqfpn36 memory mapping stm32f101xx 22/71 4 memory mapping the memory map is shown in figure 6 . figure 6. memory map 1k apb memory space dma rtc wwdg iwdg spi2 usart2 usart3 adc1 usart1 spi1 1k 35k 1k 1k 2k 1k 1k 2k 1k 1k 1k 1k 1k 7k 1k port e 1k 1k 1k 3k 1k 1k 1k 1k 1k 1k 1k 1k 2k 1k 1k 1k i2c2 exti rcc 1k 1k 1k 1k 1k 1k 1k 1k 3k 1k 3k 1k 4k 0 1 2 3 4 5 6 7 code peripherals sram reserved reserved option bytes reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4000 5400 0x4000 5800 0x4000 5c00 0x4000 6000 0x4000 6400 0x4000 6800 0x4000 6c00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4001 0800 0x4001 0c00 0x4001 1000 0x4001 1400 0x4001 1800 0x4001 1c00 0x4001 2400 0x4001 2800 0x4001 2c00 0x4001 3000 0x4001 3400 0x4001 3800 0x4001 3c00 0x4002 0000 0x4002 0400 0x4002 1000 0x4002 1400 0x4002 2000 0x4002 2400 0x4002 3000 0x4002 3400 0x6000 0000 0xe010 0000 0xffff ffff reserved reserved reserved reserved reserved reserved flash interface reserved reserved reserved reserved reserved reserved reserved port d port c port b port a afio pwr bkp reserved reserved reserved reserved i2c1 reserved reserved reserved reserved tim4 tim3 tim2 0xffff ffff 0xffff f000 0xe010 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0x1fff ffff 0x1fff f80f 0x1fff f800 0x1fff f000 0x0801 ffff 0x0800 0000 system memory flash memory cortex-m3 internal peripherals ai14379 stm32f101xx electrical characteristics 23/71 5 electrical characteristics 5.1 test conditions unless otherwise specified, all voltages are referred to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . electrical characteristics stm32f101xx 24/71 5.1.6 power supply scheme figure 9. power supply scheme figure 7. pin loading conditions figure 8. pin input voltage ai14123 c=50pf stm32f101 pin ai14124 stm32f101 pin v in ai14125 3.3v v dd 1/2/3/4/5 an alo g: rcs, pll, ... po wer swi tch v bat 3.3 v gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (osc32k,rtc, backup registers) wake-up logic 5 100 nf + 1 10 f 1.8-3.6v regulator v ss 1/2/3/4/5 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 10 nf + 1 f v ref 10 nf + 1 f v dd stm32f101xx electrical characteristics 25/71 5.1.7 current con sumption measurement figure 10. current consumption measurement scheme ai14126 v bat v dd v dda i dd _v bat i dd electrical characteristics stm32f101xx 26/71 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 4: voltage characteristics , table 5: current characteristics , and table 6: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 4. voltage characteristics symbol ratings min max unit v dd ? v ss external 3.3 v supply voltage (including v dda and v dd ) (1) 1. all 3.3 v power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external 3.3 v supply. ? 0.3 4.0 v v in input voltage on five volt tolerant pin (2) 2. i inj(pin) must never be exceeded (see table 5: current characteristics ). this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics stm32f101xx 28/71 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 9 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . . 5.3.4 embedded reference voltage the parameters given in ta bl e 1 0 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . table 9. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst pdr hysteresis 40 mv t rsttempo (1) 1. guaranteed by design, not tested in production. reset temporization 1.5 2.5 3.5 ms table 10. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 s stm32f101xx electrical characteristics 29/71 5.3.5 supply current characteristics the current consumption is measured as described in figure 10: current consumption measurement scheme . maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk/2 , f pclk2 = f hclk the parameters given in ta bl e 1 1 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . table 11. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. data based on characterization results, not tested in production. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz; external clock is 9 mhz for f hclk = 36 mhz. 72 mhz 50 ma 48 mhz 36.1 36 mhz 28.6 24 mhz 19.9 16 mhz 14.7 8 mhz 8.6 external clock (2) , all peripherals disabled 72 mhz 32.8 48 mhz 24.4 36 mhz 19.8 24 mhz 13.9 16 mhz 10.7 8 mhz 6.8 electrical characteristics stm32f101xx 30/71 figure 11. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled table 12. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max unit t a = 85 c i dd supply current in run mode external clock (1) , all peripherals enabled 72 mhz (2) 45 ma 48 mhz (3) 31.5 36 mhz (3) 24 24 mhz (3) 17.5 16 mhz (3) 12.5 8 mhz (3) 7.5 external clock (1) all peripherals disabled (3) 72 mhz 29 48 mhz 20.5 36 mhz 16 24 mhz 11.5 16 mhz 8.5 8 mhz 5.5 1. external clock is 8 mhz and pll is on when f hclk > 8 mhz; external clock is 9 mhz for f hclk = 36 mhz. 2. data based on characterization results, tested in production at v dmax , f hclk max. t amax, and code executed from ram. 3. based on characterization, not tested in production. 0 5 10 15 20 25 -40 0 25 70 85 temperature (c) consumption (ma) 36mhz 16mhz 8mhz stm32f101xx electrical characteristics 31/71 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled 0 2 4 6 8 10 12 14 16 -40 0 25 70 85 temperature (c) consumption (ma) 36mhz 16mhz 8mhz table 13. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max unit t a = 85 c i dd supply current in sleep mode external clock (1) all peripherals enabled 72 mhz (2) 28 48 mhz (3) 20 36 mhz (3) 15.5 24 mhz (3) 11.5 16 mhz (3) 8.5 8 mhz (3) 5.5 external clock (1) , all peripherals disabled (3) 72 mhz 7.5 ma 48 mhz 6 36 mhz 5 24 mhz 4.5 16 mhz 4 8 mhz 3 1. external clock is 8 mhz and pll is on when f hclk > 8 mhz; external clock is 9 mhz for f hclk = 36 mhz. 2. data based on characterization results , tested in production at v dmax , f hclk max. t amax, and code executed from ram. 3. based on characterization, not tested in production. electrical characteristics stm32f101xx 32/71 figure 13. current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v to 3.6 v table 14. typical and maximum current consumptions in stop and standby modes (1) symbol parameter conditions typ (2) max unit v dd / v bat = 2.4 v v dd / vbat = 3.3 v t a = 85 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 23.5 24 tbd (3) a regulator in low power mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 13.5 14 tbd (3) supply current in standby mode (4) low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off 1.7 2 4 (5) i dd_vbat backup domain supply current low-speed oscillator and rtc on 1 1.4 tbd (5) 1. tbd stands for to be determined. 2. typical values are measured at t a = 25 c, v dd = 3.3 v, unless otherwise specified . 3. data based on characterization results, tested in production at v dd max and f hclk max. 4. to have the standby consumption with rtc on, add i dd_vbat (low-speed oscillator and rtc on) to i dd standby (when v dd is present the backup domain is powered by v dd supply). 5. data based on characterization results, not tested in production. stop regulator on 0 20 40 60 80 100 120 140 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v stm32f101xx electrical characteristics 33/71 figure 14. current consumption in standby mode versus temperature at v dd = 3.3 v to 3.6 v standby mode 0 0.5 1 1.5 2 2.5 3 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v electrical characteristics stm32f101xx 34/71 typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk/4 , f pclk2 = f hclk/2 the parameters given in ta bl e 1 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . table 15. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled all peripherals disabled i dd supply current in run mode external clock (2) 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 19 14.8 ma 24 mhz 12.9 10.1 16 mhz 9.3 7.4 8 mhz 5.5 4.6 4 mhz 3.3 2.8 2 mhz 2.2 1.9 1 mhz 1.6 1.45 500 khz 1.3 1.25 125 khz 1.08 1.06 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 18.3 14.1 24 mhz 12.2 9.5 16 mhz 8.5 6.8 8 mhz 4.9 4 4 mhz 2.7 2.2 2 mhz 1.6 1.4 1 mhz 1.02 0.9 500 khz 0.73 0.67 125 khz 0.5 0.48 stm32f101xx electrical characteristics 35/71 table 16. typical current consumption in sleep mode, code with data processing code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled all peripherals disabled idd supply current in sleep mode external clock (2) 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 7.6 3.1 ma 24 mhz 5.3 2.3 16 mhz 3.8 1.8 8 mhz 2.1 1.2 4 mhz 1.6 1.1 2 mhz 1.3 1 1 mhz 1.11 0.98 500 khz 1.04 0.96 125 khz 0.98 0.95 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 7 2.5 24 mhz 4.8 1.8 16 mhz 3.2 1.2 8 mhz 1.6 0.6 4 mhz 1 0.5 2 mhz 0.72 0.47 1 mhz 0.56 0.44 500 khz 0.49 0.42 125 khz 0.43 0.41 electrical characteristics stm32f101xx 36/71 table 17. typical current consumption in standby mode symbol parameter conditions v dd typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit i dd supply current in standby mode (2) 2. to obtain standby consumption with rtc on, add i dd _v bat (low-speed oscillator, rtc on) to i dd standby. low-speed internal rc oscillator and independent watchdog off 3.3 v 2 a 2.4 v 1.5 low-speed internal rc oscillator and independent watchdog on 3.3 v 3.4 2.4 v 2.6 low-speed internal rc oscillator on, independent watchdog off 3.3 v 3.2 2.4 v 2.4 i dd_vbat backup domain supply current low-speed oscillator and rtc on 3.3 v 1.4 a 2.4 v 1.1 stm32f101xx electrical characteristics 37/71 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 1 8 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 4 . table 18. peripheral current consumption peripheral typical consumption at 25 c (1) 1. f hclk = 36 mhz, f apb1 = f hclk/2 , f apb2 = f hclk , default prescaler value for each peripheral. unit apb1 tim2 0.6 ma tim3 0.6 tim4 0.6 spi2 0.08 usart2 0.21 usart3 0.21 i2c1 0.18 i2c2 0.18 usb 0.32 can 0.33 apb2 gpio a 0.21 gpio b 0.21 gpio c 0.21 gpio d 0.21 gpio e 0.21 adc1 0.71 adc2 0.68 tim1 0.76 spi1 0.24 usart1 0.35 electrical characteristics stm32f101xx 38/71 5.3.6 external cloc k source characteristics high-speed user external clock the characteristics given in ta b l e 1 9 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 7 . table 19. high-speed user external (hse) clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. value based on design simulation and/or technology characteristics. it is not tested in production. 825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 16 ns t r(hse) t f(hse) osc_in rise or fall time (1) 5 i l osc_in input leakage current v ss v in v dd 1 a stm32f101xx electrical characteristics 39/71 low-speed user external clock the characteristics given in ta b l e 2 0 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 7 . figure 15. high-speed external clock source ac timing diagram table 20. low-speed user external clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. value based on design simulation and/or technology characteristics. it is not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 5 i l osc32_in input leakage current v ss v in v dd 1 a ai14127 os c _i n exter nal stm32f101 clo ck so urc e v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel electrical characteristics stm32f101xx 40/71 figure 16. low-speed external clock source ac timing diagram high-speed external clock the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 1 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14140b osc32_in exter nal stm32f101 clo ck so urc e v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel table 21. hse 4-16 mhz oscillator characteristics (1) symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k ? c l1 c l2 (2) recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) r s = 30 ? 30 pf i 2 hse driving current v dd = 3.3 v v in = v ss with 30 pf load 1ma g m (4) oscillator transconductance startup 25 ma/v t su(hse) (5) startup time v ss is stabilized 2 ms 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. for c l1 and c l2 it is recommended to use high-qualit y ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match t he requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance wh ich is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). 3. the relatively low value of the rf resistor offers a good protection against issues resu lting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. 4. based on characterization results, not tested in production. 5. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stab ilized 8 mhz os cillation is reached. this value is measured for a standa rd crystal resonator and it can vary signi ficantly with the crystal manufacturer stm32f101xx electrical characteristics 41/71 figure 17. typical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. typical value is in the range of 5 to 6r s . low-speed external clock the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 2 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). figure 18. typical application with a 32.768 khz crystal table 22. lse oscillator characteristics ( f lse = 32.768 khz) symbol parameter conditions min typ max unit r f feedback resistor 5 m ? c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (1) 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768 khz. refer to crystal manufacturer for more details r s = 30 k ? 15 pf i 2 lse driving current v dd = 3.3 v v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (2) 2. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v ss is stabilized 3 s ai14128 osc_ou t osc_in f hse c l1 r f stm32f101xx 8 mh z resonator resonator with in tegrated capac itors bias controlled gain r ext (1) c l2 ai14129 osc32_ou t osc32_in f lse c l1 r f stm32f101xx 32.768 kh z resonator resonator with in tegrated capac itors bias controlled gain c l2 electrical characteristics stm32f101xx 42/71 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 3 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . high-speed internal (hsi) rc oscillator lsi low speed internal rc oscillator table 23. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ? 40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz acc hsi accuracy of hsi oscillator t a = ?40 to 85 c (2) 2. values based on device characte rization, not tested in production. 3% at t a = 25 c 1 2% t su(hsi) hsi oscillator startup time 1 2 s i dd(hsi) hsi oscillator power consumption 80 100 a table 24. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ? 40 to 85 c unless otherwise specified. symbol parameter conditions min (2) 2. value based on device characteri zation, not tested in production. typ max unit f lsi frequency 30 40 60 khz t su(lsi) lsi oscillator start up time 85 s i dd(lsi) lsi oscillator power consumption 0.65 1.2 a stm32f101xx electrical characteristics 43/71 wakeup time from low power mode the wakeup times given in ta b l e 2 5 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 7 . 5.3.8 pll characteristics the parameters given in ta bl e 2 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 7 . table 25. low-power mode wakeup timings (1) 1. tbd stands for to be determined. symbol parameter conditions typ max unit t wusleep (2) 2. the wakeup times are measured from the wakeup even t to the point at which the user application code reads the first instruction. wakeup from sleep mode wakeup on hsi rc clock 1.8 tbd s t wustop (2) wakeup from stop mode (regulator in run mode) hsi rc wakeup time = 2 s 3.6 tbd s wakeup from stop mode (regulator in low-power mode) hsi rc wakeup time = 2 s, regulator wakeup from lp mode time = 5 s 5.4 9 t wustdby (2) wakeup from standby mode hsi rc wakeup time = 2 s, regulator wakeup from power down time = 38 s 50 150 s table 26. pll characteristics symbol parameter test conditions value unit min typ max (1) 1. data based on device characterization, not tested in production. f pll_in pll input clock 8.0 mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 36 mhz t lock pll lock time 200 s electrical characteristics stm32f101xx 44/71 5.3.9 memory characteristics flash memory the characteristics are given at t a = ? 40 to 85 c unless otherwise specified. table 28. flash endurance and data retention table 27. flash memory characteristics (1) 1. tbd stands for to be determined. symbol parameter conditions min typ max (2) 2. values based on characterization and not tested in production. unit t prog word programming time t a = ? 40 to +85 c 20 40 s t erase page (1kb) erase time t a = ? 40 to +85 c 20 40 ms t me mass erase time t a = ? 40 to +85 c 20 40 ms i dd supply current read mode f hclk = 36mhz with 2 wait states, v dd = 3.3 v 20 ma write / erase modes f hclk = 36 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd =3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v symbol parameter conditions value unit min (1) 1. values based on characterization not tested in production. typ max n end endurance 10 kcycles t ret data retention t a = 85 c 30 years stm32f101xx electrical characteristics 45/71 5.3.10 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 2 9 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in rela tion with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 29. ems characteristics (1) 1. tbd stands for to be determined. symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100 2b v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100 4a electrical characteristics stm32f101xx 46/71 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with sae j 1752/3 standard which specifies the test board and the pin loading. 5.3.11 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size is either 3 parts (cumulative mode) or 3 parts (n + 1) supply pins (non-cumulative mode). the human body model (hbm) can be simulated. the tests are compliant with jesd22- a114a standard. for more details, refer to the application note an1181. table 30. emi characteristics (1) 1. tbd stands for to be determined. symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/36 mhz s emi peak level v dd = 3.3 v, t a = 2 5c, lqfp100 package compliant with sae j 1752/3 0.1 mhz to 30 mhz 7 dbv 30 mhz to 130 mhz 8 130 mhz to 1ghz 13 sae emi level 3.5 - table 31. esd absolute maximum ratings (1) 1. tbd stands for to be determined. symbol ratings conditions maximum value (2) 2. values based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 500 stm32f101xx electrical characteristics 47/71 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78 ic latch-up standard. 5.3.12 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 3 3 are derived from tests performed under the conditions summarized in ta b l e 7 . all i/os are cmos and ttl compliant. all unused pins must be configured in either of the three modes below: as outputs with an external pull-up or pull-down resistor and held at a fixed voltage (see figure 19 ) as push-pull outputs with 0 written into the data register or as analog inputs table 32. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c ii level a table 33. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage (1) ttl ports ?0.5 0.8 v v ih standard io input high level voltage (1) 2v dd +0.5 io ft (2) input high level voltage (1) 25.5v v il input low level voltage (1) cmos ports ?0.5 0.35 v dd v v ih input high level voltage (1) 0.65 v dd v dd +0.5 v hys standard io schmitt trigger voltage hysteresis (3) 200 mv io ft schmitt trigger voltage hysteresis (3) 5% v dd (4) mv i lkg input leakage current (4) v ss v in v dd standard i/os 1 a v in = 5 v i/o ft 3 r pu weak pull-up equivalent resistor (5) v in = v ss 30 40 50 k ? electrical characteristics stm32f101xx 48/71 figure 19. unused i/o pin connection output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink +20 ma (with a relaxed v ol ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 5 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 5 ). r pd weak pull-down equivalent resistor (6) v in = v dd 30 40 50 k ? c io i/o pin capacitance 5 pf 1. values based on characterization re sults, and not tested in production. 2. ft = five-volt tolerant. 3. hysteresis voltage between schmitt trigger switching levels. based on c haracterization results, not tested. 4. with a minimum of 100 mv. 5. leakage could be higher than max. if negativ e current is injected on adjacent pins. 6. pull-up and pull-down resistors are designed with a true resistance in seri es with a switchable pmos/nmos. this pm os/nmos contribution to the series resistance is minimum (~10% order) . table 33. i/o static characteristics (continued) symbol parameter conditions min typ max unit ai14130 10 k ? 10 k ? unu sed i/o port stm32f101 v dd unu sed i/o port stm32f101 stm32f101xx electrical characteristics 49/71 output voltage levels unless otherwise specified, the parameters given in ta bl e 3 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 7 . all i/os are cmos and ttl compliant. table 34. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 5 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port, i io = +8 ma, 2.7 v < v dd < 3.6 v 0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 5 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 4 pins are sourced at same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma (3) 2.7 v < v dd < 3.6 v 3. based on characterization data, not tested in production. 1.3 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma (3) 2 v < v dd < 2.7 v 0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 electrical characteristics stm32f101xx 50/71 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 20 and ta bl e 3 5 , respectively. unless otherwise specified, the parameters given in ta bl e 3 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 7 . table 35. i/o ac characteristics (1) 1. the i/o speed is configured using t he modex[1:0] bits. refer to the stm32f10x reference manual for a description of gpio port configuration register. modex [1:0] bit value (1) symbol parameter conditions max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 20 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. values based on design simulation and va lidated on silicon, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns stm32f101xx electrical characteristics 51/71 figure 20. i/o ac characteristics definition 5.3.13 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 3 3 ). unless otherwise specified, the parameters given in ta bl e 3 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 7 . figure 21. recommended nrst pin protectio n 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 36 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 36. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage ?0.5 0.8 v v ih(nrst) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 r pu weak pull-up equivalent resistor (1) 1. the pull-up is designed with a true resistance in series with a switc hable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k ? v f(nrst) nrst input filtered pulse (2) 2. values guaranteed by design, not tested in production. 100 ns v nf(nrst) nrst input not filtered pulse (2) 300 s ai14132b stm32f10xxx r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1) electrical characteristics stm32f101xx 52/71 5.3.14 tim time r characteristics the parameters given in ta bl e 3 7 are guaranteed by fabrication. refer to section 5.3.12: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). 5.3.15 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 3 8 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 7 . the stm32f101xx access line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: t he i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. in addition, there is a protection diode between the i/o pin and v dd . as a consequence, when multiple master devices are connected to the i 2 c bus, it is not possible to powe r off the stm32f101xx while another i 2 c master node remains powered on. otherwise, the st device would be powered by the protection diode. the i 2 c characteristics are described in ta b l e 3 8 . refer also to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 37. timx characteristics symbol parameter timx (1) 1. x gives the tim concerned; where x = 2, tim2 is concerned, etc. conditions min max unit t res(tim) timer resolution time x = 2, 3, 4 1 t timxclk f timxclk = 36 mhz 27.8 ns f ext timer external clock frequency on ch1 to ch4 x = 2, 3, 4 0 f timxclk /2 mhz f timxclk = 36 mhz 018mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected x = 2, 3, 4 1 65536 t timxclk f timxclk = 36 mhz 0.0278 1820 s t max_count maximum possible count x = 2, 3, 4 65536 65536 t timxclk f timxclk = 36 mhz 119.2 s stm32f101xx electrical characteristics 53/71 table 38. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. values based on standard i 2 c protocol requirement, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 4 mhz to achieve the maximum fast mode i 2 c frequency. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf electrical characteristics stm32f101xx 54/71 figure 22. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 39. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) (1)(2)(3) 1. tbd = to be determined. 2. r p = external pull-up resistance, f scl = i 2 c speed, 3. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k ? 400 tbd 300 tbd 200 tbd 100 tbd 50 tbd 20 tbd ai14127b start sd a 100 ? 4.7k ? i2c bus 4.7k ? 100 ? v dd v dd stm32f101 sda scl t f(sda) t r(sda) scl t h(sta) t w(sckh) t w(sckl) t su(sda) t r(sck) t f(sck) t h(sda) s tart repeated start t su(sta) t su(sto) s top t su(sta:sto) stm32f101xx electrical characteristics 55/71 spi interface characteristics unless otherwise specified, the parameters given in ta bl e 4 0 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 7 . refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 40. spi characteristics (1) 1. tbd = to be determined. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode tbd tbd mhz slave mode 0 tbd t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 50 pf tbd ns t su(nss) (2) 2. values based on design simulation and/or charac terization results, and not tested in production. nss setup time slave mode 0 t h(nss) (2) nss hold time slave mode (3) 3. values based on device characte rization, not tested in production. 0 t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f pclk = tbd, presc = tbd tbd t su(mi) (2) t su(si) (2) data input setup time master mode tbd slave mode tbd t h(mi) (2) t h(si) (2) data input hold time master mode tbd slave mode tbd master mode, f pclk = tbd tbd (4) 4. depends on f pclk . for example, if f pclk = 8 mhz, then t pclk = 1/f plclk =125 ns and t v(mo) = 255 ns. slave mode, f pclk = tbd tbd (4) t a(so) (2)(5) 5. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode tbd tbd slave mode, f pclk = tbd tbd tbd t dis(so) (2)(6) 6. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode tbd tbd t v(so) (2)(1) data output valid time slave mode (after enable edge) tbd f pclk = tbd tbd t v(mo) (2)(1) data output valid time master mode (after enable edge) tbd f pclk = tbd tbd tbd t h(so) (2) data output hold time slave mode (after enable edge) tbd t h(mo) (2) master mode (after enable edge) tbd electrical characteristics stm32f101xx 56/71 figure 23. spi timing diagram - slave mode and cpha=0 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . figure 24. spi timing diagram - slave mode and cpha=1 1) ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32f101xx electrical characteristics 57/71 figure 25. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32f101xx 58/71 5.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 4 1 are derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 7 . note: it is recommended to perform a calibration after each power-up. table 41. adc characteristics symbol parameter conditions min typ max unit v dda adc power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v f adc adc clock frequency 0.6 14 mhz f s sampling rate tbd (1) 1. tbd = to be determined. 0.05 1 mhz f trig external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range 0 (v ssa or v ref- tied to ground) v ref+ v r ain external input impedance see equation 1 and ta b l e 4 2 k ? i lkg negative input leakage current on analog pins v in < v ss, | i in |< 400 a on adjacent analog pin 56a r adc sampling switch resistance 1k ? c adc internal sample and hold capacitor 5pf t cal calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (2) 2. for internal triggers, a delay of 1/f pclk2 must be added to the latency specified in table 41 . 1/f adc t latr regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (2) 1/f adc t s sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab power-up time 0 0 1 s t conv total conversion time (including sampling time) f adc = 14 mhz 118s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc stm32f101xx electrical characteristics 59/71 equation 1: r ain max formula: the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 42. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k ? ) 1.5 0.11 1.2 7.5 0.54 10 13.50.9619 28.52.0441 41.52.9660 55.53.9680 71.55.11104 239.5 17.1 350 table 43. adc accuracy (1) 1. adc dc accuracy values are m easured after internal calibration. symbol parameter test conditions typ (2) 2. data based on characterization, not tested in production. max (2) unit et total unajusted error f pclk2 = 28 mhz, f adc = 14 mhz, r ain <10 k ? , v dda = 2.4 v to 3.6 v measurements made after adc calibration v ref+ = v dda 35 lsb eo offset error 1 3 eg gain error 1 2 ed differential linearity error 3 3 el integral linearity error 2 4 r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < electrical characteristics stm32f101xx 60/71 figure 26. adc accura cy characteristics figure 27. typical connection diagram using the adc 1. refer to table 41 for the values of r ain , r adc and c adc . 2. c parasitic must be added to c ain . it represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (3 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 28 or figure 29 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = ai14139b stm32f101 v dd ainx i l 1 a 0.6 v v t r ain (1) c ain v ain 0.6 v v t r adc (1) 12-bit a/d conversion c adc (1) stm32f101xx electrical characteristics 61/71 figure 28. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. figure 29. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. 5.3.17 temperature sen sor characteristics v ref+ stm32f101xx v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai14380 v ref+ /v dda stm32f101xx 1 f // 10 nf v ref? /v ssa ai14380 table 44. ts characteristics symbol parameter conditions min typ max unit t l v sense linearity with temperature 1.5 c avg_slope average slope 4.478 mv/c v 25 voltage at 25c 1.4 v electrical characteristics stm32f101xx 62/71 t start startup time 4 10 s t s_temp (1) adc sampling time when reading the temperature 2.2 17.1 s 1. shortest sampling time can be determined in the application by multiple iterations. table 44. ts characteristics symbol parameter conditions min typ max unit stm32f101xx package characteristics 63/71 6 package characteristics in order to meet environmental requirements, st offers the stm32f101xx in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 30. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. table 45. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 d 5.875 6.000 6.125 0.2313 0.2362 0.2411 d2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 5.875 6.000 6.125 0.2313 0.2362 0.2411 e2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 l 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 seating plane ddd c c a3 a1 a a2 d e 28 36 pin # 1 id r = 0.20 27 1 e 9 l 10 18 d2 19 b e2 zr_me package characteristics stm32f101xx 64/71 figure 31. lqpf100 ? 100-pin low-profile quad flat package outline 1. drawing is not to scale. table 46. lqpf100 ? 100-pin low-profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 16.00 0.6299 d1 14.00 0.5512 e 16.00 0.6299 e1 14.00 0.5512 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n 100 h c l l 1 e b a a 2 a1 d d1 e e 1 ai14382 stm32f101xx package characteristics 65/71 figure 32. lqfp64 ? 64-pin low-profile quad flat package outline 1. drawing is not to scale. table 47. lqfp64 ? 64-pin low-profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n64 a a2 a1 c l1 l e e1 d d1 e b ai14383 package characteristics stm32f101xx 66/71 figure 33. lqfp48 ? 48-pin low-profile quad flat package outline 1. drawing is not to scale. table 48. lqfp48 ? 48-pin low-profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n48 e e1 d d1 l1 l c e b a1 a2 a ai14384 stm32f101xx package characteristics 67/71 6.1 thermal characteristics the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja ) (1) where: t a is the ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o (p d = p int + p i/o ), p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; most of the time for the application p i/o < p int and can be neglected. on the other hand, p i/o may be significant if the device is configured to drive continuously external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273 c) + ja x p d 2 (3) where: k is a constant for the particular part, which may be determined from equation (3) by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a . table 49. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 100 - 14 x 14 mm / 0.5 mm pitch 46 c/w thermal resistance junction-ambient lqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient lqfp 48 - 7 x 7 mm / 0.5 mm pitch 55 order codes stm32f101xx 68/71 7 order codes 7.1 future family enhancements further developments of t he stm32f101xx access line will see an expansion of the current options. larger packa ges will soon be available with up to 512kb flash, 48kb sram and with extended features such as emi support, dac and additional timers and usarts. table 50. order codes partnumber flash program memory (kbytes) sram memory (kbytes) package stm32f101t6u6 32 6 vfqfpn36 stm32f101t8u6 64 10 stm32f101c6t6 32 6 lqfp48 stm32f101c8t6 64 10 stm32f101cbt6 128 16 stm32f101r6t6 32 6 lqfp64 stm32f101r8t6 64 10 STM32F101RBt6 128 16 stm32f101v8t6 64 10 lqfp100 stm32f101vbt6 128 16 stm32f101xx important notes 69/71 appendix a important notes the notes listed below apply to stm32f101xx devices revision z. for more details on how to identify the device revision, please refer to section 20.6.1 mcu device id code in the stm32f10xxx reference manual. a.1 pd0 and pd1 use in output mode the use of pd0 and pd1 in output mode is limited as in this mode, pd0 and pd1 can only be used at 50 mhz. a.2 adc auto-injection channel when the adc clock prescaler ranges from 4 to 8, a delay of 1 adc clock period is automatically inserted when switching from regular to injected conversion (and conversely, from injected to regular). when the adc clock pr escaler is set to 2, the delay is 2 adc clock periods. a.3 adc combined injected simultaneous + interleaved when the adc clock prescaler is set to 4, the interleaved mode does not recover with evenly spaced sampling periods: the sampling interval is 8 adc clock periods followed by 6 adc clock periods, instead of 7 clock periods followed by 7 clock periods. a.4 voltage glitch on adc input 0 a low-amplitude voltage glitch can be generated on adc input 0, when the adc is converting with injection trigger, in very specific cases. it is generated by internal coupling and synchronized to the beginning and the end of the injection sequence, whatever the channel(s) to be converted. it has an amplitude of less than 150 mv and a typical duration of 10 ns (measured with the i/o left unconnected). this has no influence on the digital output signals or the digital inputs, providing that they are driven with a reasonably low impedance. revision history stm32f101xx 70/71 revision history table 51. document revision history date revision changes 06-jun-2007 1 first draft. 20-jul-07 2 i dd values modified in table 11: maximum current consumption in run and sleep modes (ta = 85 c) . v bat range modified in power supply schemes . v ref+ min value, t stab , t lat and f trig added to table 41: adc characteristics . table 37: timx characteristics modified. note 5 modified and note 7 , note 4 and note 6 added below ta b l e 3 : p i n definitions . figure 16: low-speed external clock source ac timing diagram , figure 9: power supply scheme , figure 21: recommended nrst pin protection and figure 22: i 2 c bus ac waveforms and measurement circuit modified. sample size modified and machine model removed in electrostatic discharge (esd) . number of parts modified and standard reference updated in static latch- up . 25 c and 85 c conditions removed and class name modified in table 32: electrical sensitivities . t su(lse) changed to t su(lse) in table 21: hse 4-16 mhz oscillator characteristics . in table 28: flash endurance and data retention , typical endurance added, data retention for t a = 25 c removed and data retention for t a = 85 c added. note removed below table 7: general operating conditions . v bg changed to v refint in table 10: embedded internal reference voltage . i dd max values added to table 11: maximum current consumption in run and sleep modes (ta = 85 c) . i dd(hsi) max value added to table 23: hsi oscillator characteristics . r pu and r pd min and max values added to table 33: i/o static characteristics . r pu min and max values added to table 36: nrst pin characteristics (two notes removed). datasheet title corrected. usb characteristics section removed. features on page 1 list optimized. small text changes. stm32f101xx revision history 71/71 18-oct-2007 3 v esd(cdm) value added to table 31: esd absolute maximum ratings . note added below table 9: embedded reset and power control block characteristics . and below table 21: hse 4-16 mhz oscillator characteristics . note added below table 34: output voltage characteristics and v oh parameter description modified. table 41: adc characteristics and table 43: adc accuracy modified. figure 26: adc accuracy characteristics modified. packages are ecopack? compliant. tables modified in section 5.3.5: supply cu rrent characteristics . adc and anti_tamper signal names modified (see ta b l e 3 : p i n definitions ). table 3: pin definitions modified. note 4 removed and values updated in table 17: typical current co nsumption in standby mode . v hys modified in table 33: i/o static characteristics . updated: table 29: ems characteristics and ta bl e 3 0 : e m i characteristics . t vdd modified in table 8: operating conditions at power-up / power-down . typical values modified, note 2 modified and note 3 removed in table 25: low-power mode wakeup timings . maximum current consumption ta bl e 1 1 , ta bl e 1 2 and ta bl e 1 3 updated. values added and notes added in table 14: typical and maximum current consumptions in stop and standby modes . on-chip peripheral current consumption on page 37 added. package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see section 6: package characteristics ). v prog added to table 27: flash memory characteristics . t s_temp added to table 44: ts characteristics . t s_vrefint added to table 10: embedded internal reference voltage . handling of unused pins specified in general input/output characteristics on page 47 . all i/os are cmos and ttl compliant. table 3: pin definitions : table clarified and note 6 modified. internal lsi rc frequency changed from 32 to 40 khz (see table 24: lsi oscillator characteristics ). values added to table 25: low-power mode wakeup timings . n end modified in table 28: flash endurance and data retention . option byte addresses corrected in figure 6: memory map . acc hsi modified in table 23: hsi oscillator characteristics . t jitter removed from table 26: pll characteristics . appendix a: important notes on page 69 added. added: figure 11 , figure 12 , figure 13 and figure 14 . table 51. document revision history (continued) date revision changes stm32f101xx 71/71 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no 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